Semiconductor device

ABSTRACT

A semiconductor device of the invention in the form of a superlattice-heterojunction bipolar transistor (SL-HBT)  10  incorporates a superlattice region  16  within an emitter mesa  21.  The superlattice region  16  provides a non-linear response to a sufficiently high level of device current to counteract thermal runaway. This protects the device from damaging levels of current. The device  10  may be a radio-frequency SL-HBT with performance equivalent to that of a conventional heterojunction bipolar transistor. The invention may also be implemented as a semiconductor laser.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor device with current limitingproperties, and more particularly (although not exclusively) to atransistor or a vertical-cavity surface-emitting laser (VCSEL).

2. Discussion of Prior Art

Thermal runaway has been a known problem in semiconductor devices sincethe 1950s. It is particularly relevant to devices composed of narrowbandgap materials operated at ambient temperature and those of widerbandgap materials operated at elevated temperatures (eg high powerdevices). It results from device resistance falling with an increase intemperature, device current increasing in consequence, temperatureincreasing and resistance falling further and so on. It can lead tocatastrophic device failure.

One form of semiconductor device incorporates an electrically parallelarray of current-carrying elements intended to carry like currents, andin this device small growth or fabrication non-uniformities amongstindividual elements can lead to localised heating during operation. Thisresults in an individual element of the device carrying most of thecurrent through the device by the process of thermal runaway. Examplesof such semiconductor devices are multi-finger bipolar power transistorsand VCSEL arrays. If a localised defect should induce an increase ofcurrent in a particular part of the device, an increase in temperaturewill be produced which in turn induces further increments in thelocalised current by increasing the number of charge carriers. Positiveelectrical and thermal feedback in a locality results in a non-uniformcurrent distribution amongst the various elements, causing failure ofthe device as a whole, and may also lead to the destruction of theindividual element concerned. The effect whereby a single elementconducts most of the current through a device is known as“current-hogging”.

In the case of an array of electrically-parallel VCSELs, thecurrent-hogging problem may lead to catastrophic damage in individuallasers which have a lower resistance than the other members of thearray. Variations in the resistances of these lasers also result invariations in the currents conducted by them, and hence to non-uniformbrightness across the array.

In the context of bipolar transistors, the current-hogging problem hasmeant that multi-finger devices have been unreliable during high-poweroperation in the absence of stabilisation schemes to eliminate theproblem of thermal runaway. Current-hogging by a single emitter fingercauses failure of the entire transistor, i. e. a collapse in currentgain, output power, and available voltage swing during radio-frequency(RF) operation. Permanent damage may occur to the current-hoggingemitter finger.

Several current stabilisation schemes for multi-finger power transistorshave been proposed. One such scheme involves the integration of a fixedstabilising resistor, or “ballast resistor”, into the structure in orderto limit the current flowing through any single finger. Fixed ballastresistors have been integrated into the emitter and base regions oftransistors, as reported by Gao et al and Liu et at in the IEEETransactions on Electron Devices, Volume 21, No. 7, 1991 and Volume 38,No. 2, 1996 respectively. However such designs have the disadvantagethat under low current and/or temperature conditions, there is asignificant penalty to the RF power efficiency of the transistor becausecurrent is limited through all the fingers of the device simultaneously,including those fingers which do not have the problem of thermalrunaway.

In another stabilisation scheme, known as thermal shunting, the emitterfingers of a transistor are thermally coupled to each other by a metalbridge in order to reduce temperature non-uniformities. In IEEE ElectronDevice Letters, Volume 17, No. 1, 1996, an example of athermally-shunted bipolar transistor was disclosed by Sewell et al. Inyet another scheme, disclosed at the 1994 IEEE International ElectronDevices Meeting by Yang et al, a recess is etched into the reverse sideof the substrate opposite the active layers, and metallised to form aheatsink. Schemes such as these involve many processing steps inaddition to wafer growth and processing, significantly increasing theoverall processing time and cost.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an alternative form ofsemiconductor device in which current is limited.

The present invention provides a transistor comprising an emitterincorporating a superlattice structure, a base and a collectorcharacterised in that the transistor has an emitter-current versusbase-emitter voltage characteristic which exhibits a first region belowa critical emitter-current and having a non-zero slope of average valuem₁, a reduction in slope from the value m₁ at the criticalemitter-current; and a current plateau above the criticalemitter-current, the plateau having an average slope m₂ in the range−0.05 m₁≦m₂≦+0.05 m₁.

The invention provides the advantage that a current-carrying elementwithin a semiconductor device of the invention is protected from thermalrunaway. Also, in a semiconductor device of the invention having aplurality of electrically parallel current carrying elements (forexample a multi-finger transistor or a VCSEL array) the inventionprovides the advantage that any current-hogging by one or more elementsof the device, and hence imbalance in current distribution within thedevice, is counteracted . This is achieved by increases in theresistances of those elements which begin to draw abnormally highcurrents without changing the resistances of, or currents in, theremaining elements. Unnecessary reductions in the currents carried bythe remaining elements are therefore avoided and the functioning ofthese elements is unaffected. The risk of catastrophic damage to anelement which begins to draw an abnormally high current is reduced.

A current-carrying element of a device of the invention has a non-linearcurrent versus voltage characteristic. More specifically, acurrent-carrying element of a device of the invention has a differentialresistance which is substantially constant up to a critical current, andthen increases very rapidly with increasing current to a much greatervalue. Current-carrying elements of devices of the invention aretherefore protected against thermal runaway.

Devices of the invention may be entirely fabricated using epitaxialgrowth methods and processing methods familiar to those skilled in theart of semiconductor device fabrication.

A device of the invention has a further advantage over a prior artdevice incorporating a fixed ballast resistor. The superlatticestructure is typically ten times thinner than such a resistor, providinga shorter heat-conducting path from the active region of thesemiconductor device to the contact metallisation. The resultingimprovement in heat dissipation increases the lifetime of the device andreduces its susceptibility to thermal runaway.

Devices of the invention in the form of bipolar transistors may be usedin radio frequency (RF) amplifying circuits. They can provide a currentlimit within the natural current limit of the transistor, and hencecurrent-clipping of the input waveform, which makes it possible toachieve very high efficiency RF amplification. Presently,current-clipping is achieved in RF amplifiers by driving the transistorto its natural saturation current, resulting in charge storage in thetransistor which severely degrades the gain bandwidth of the amplifier.

A semiconductor device of the invention may be in the form of aheterojunction bipolar transistor device in which the superlatticestructure adjoins a first active region and forms an emitter incombination with the first active region and a second active regioncomprises both the base and collector, the second active regionadjoining the first active region at a side thereof opposite to thatadjoining the superlattice structure.

A semiconductor device of the invention may be in the form of asemiconductor laser having first and second active regions, the firstactive region including an optical gain layer and the superlatticestructure adjoining the first active region at a side thereof oppositeto that adjoining the second active region. The optical gain layer mayhave optical cladding. The device may be replicated to form an array oflasers. It may be constructed at least partly of layers of theAl_(x)Ga_(1−x)As material system, where 0≦x≦1.

A semiconductor device of the invention may have a plurality ofindividual first active regions all adjoining a second active region,and the superlattice structure may comprise individual superlatticestructures each adjoining a respective first active region and eachhaving a current versus voltage characteristic which exhibits a changein resistance at a critical current to prevent current within acorresponding first active region from reaching an undesirable level. Itmay be a heterojunction bipolar transistor device having base, collectorand emitter elements, each superlattice structure forming an emitterelement in combination with a respective first active region, the secondactive region comprising both base and collector elements and eachsuperlattice structure adjoining a respective first active region at aside thereof opposite to that adjoining the second active region. Thetransistor base element may be of InGaP and other device parts may be ofthe Al_(x)Ga_(1−x)As material system, where x=0, 0.15 or 0.33.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the invention may be more fully understood, embodimentsthereof will now be described, by way of example only, with reference tothe accompanying drawings in which:

FIG. 1 schematically illustrates a vertical cross-section of asuperlattice-heterojunction bipolar transistor (SL-HBT) of theinvention,

FIG. 2 is a table giving details of the layer structure of the FIG. 1device,

FIG. 3 schematically illustrates the relative lateral positions of metalcontacts of the FIG. 1 device,

FIGS. 4 to 10 schematically illustrate principal wafer processing stepsin the fabrication of the FIG. 1 device,

FIG. 11 is a vertical section through a heterojunction bipolartransistor (HBT) of the invention,

FIG. 12 is a table giving details of the layer structure of the FIG. 11device,

FIG. 13 graphically illustrates the base-emitter junctioncharacteristics of five SL-HBT devices,

FIG. 14 graphically illustrates variations of the collector current withcollector-emitter bias for a SL-HBT for various values of base current,

FIGS. 15 to 22 graphically illustrate the variations of maximumoscillation frequency, maximum available gain, dynamic emitterresistance and base-emitter voltage with collector current density for aSL-HBT and a HBT,

FIG. 23 graphically illustrates variations in the gain, power addedefficiency, collector efficiency and collector current with output powerfor a SL-HBT, and

FIG. 24 is a vertical section through a superlattice-vertical-cavitysurface-emitting laser (SL-VCSEL), which is a device of the invention.

DETAILED DISCUSSION OF EMBODIMENTS

Referring to FIG. 1, there is shown a semiconductor device of theinvention in the form of a superlattice—heterojunction bipolartransistor (SL-HBT) indicated generally by 10. The SL-HBT 10incorporates successively disposed semiconductor layers, the first layer11 (a subcollector layer) being in contact with a 500 μm thick undopedGaAs substrate (not shown), and each subsequent layer 12 to 17 being incontact and forming a junction with two respective layers adjacent toit. Details of the layers are as follows:

a subcollector layer 11,

a collector layer 12,

a base layer 13,

an emitter layer 14,

an emitter electrode layer 15,

layers 16 a to 16 f, 16 g ₁, 16 h ₁, 16 g ₂, 16 h ₂, . . . 16 g ₂₅, 16 h₂₅ constituting a

superlattice region 16, and

an electrode layer 17.

The SL-HBT 10 also incorporates the following metal contacts:

a metal emitter contact 18 in contact with the electrode layer 17,

a metal base contact 19 in contact with the base layer 13, and

a metal collector contact 20 in contact with the subcollector layer 11.

In combination, layers 14 to 17 and the metal emitter contact 18constitute an emitter mesa 21.

FIG. 2 is a table giving the thickness, composition and doping densityof each of the layers 11 to 17. The pair of layers 16 g ₁, 16 h ₁ isreplicated 24 times, forming the layers 16 g ₂, 16 h ₂, 16 g ₃, 16 h ₃,. . . 16 g ₂₅, 16 h ₂₅. Layers 16 g ₂, 16 g ₃, . . . 16 g ₂₅ have thesame parameters of thickness, composition, doping material and dopingdensity as layer 16 g ₁ ignoring variations associated with processinginaccuracies. Layers 16 h ₂, 16 h ₃, . . . 16 h ₂₅ have the sameparameters as layer 16 h ₁ in these respects. Layers 16 g ₁, 16 g ₂, . .. 16 g ₂₅ are quantum well layers and layers 16 f and 16 g ₁, 16 g ₂, .. . 16 g ₂₅ are their associated barrier layers. A quantum well layerand an adjacent barrier layer have a difference in conduction band edgeenergy known as a barrier height.

The layers 11 to 13 and 15 to 17 are all derived from theAl_(x)Ga_(1−x)As material system, where x=0, 0.15 or 0.33. The emitterlayer 14 is of InGaP lattice-matched to the GaAs base layer 13.

The metal emitter contact 18 consists of the following successive layers(not shown in detail) each in contact with the next, the first being incontact with the electrode layer 17:

a 5 nm thick layer of nickel,

a 20 nm thick layer of germanium, and

a 480 nm thick layer of gold.

The metal base contact 19 consists of the following successive layers(not shown in detail), each in contact with the next, the first being incontact with the base layer 13:

a 75 nm thick layer of titanium,

a 75 nm thick layer of palladium, and

a 200 nm thick layer of gold.

The metal collector contact 20 has the same composition and structure asthe metal emitter contact 18.

Referring now to FIG. 3, there is shown a plan view of the SL-HBT 10,indicating the lateral positions of the metal emitter contact 18, themetal base contact 19, and the metal collector contact 20. The metalemitter contact 18 is rectangular and has a width t of 3 μm and a lengthe of 30 μm. The metal base contact 19 is U-shaped; it has a width c of 2μm and surrounds the metal emitter contact 18 as shown. The separation bof the metal emitter contact 18 and the metal base contact 19 is 1.5 μm.The metal collector contact 20 has a width d of 10 μm and a length f of33.5 μm, and is separated from the metal base contact 19 by a distance cof 2 μm.

The fabrication of the SL-HBT 10 has two principal stages, namely wafergrowth and wafer processing. In the wafer growth stage, the layerstructure of the SL-HBT 10 is deposited on a 500 μm thick undoped GaAssubstrate in the order shown in the table in FIG. 2. Layers 11 to 16 aare laid down by metal-organic vapour-phase epitaxy (MOVPE). MOVPEgrowth is stopped after layer 16 a, and the wafer is transferred to amolecular beam epitaxy (MBE) reactor. Layers 16 b to 17 are deposited byMBE. Layer 16 b is an n-type doping layer consisting of a partialsingle-atomic layer of silicon having an areal density of 2×10¹² atomscm⁻².

The wafer processing stage defines the lateral structure of the SL-HBT10, and is carried out using known techniques of photolithography, dryetching and wet etching. The first step in the wafer processing stage,illustrated in FIG. 4, is the deposition of the metal emitter contact 18onto the electrode layer 17 by electron-beam evaporation. The wafer isthen dry-etched down to 50 to 100 nm above the emitter layer 14 toproduce a first portion of the emitter mesa 21, as shown in FIG. 5. Aselective wet chemical etchant is used to etch down to the emitter layer14 and to under-cut the first portion of the emitter mesa 21 asindicated in FIG. 6. Referring to FIG. 7, a selective wet chemicaletchant is then used to etch through the emitter layer 14, stopping atthe base layer 13 to complete the emitter mesa 21. The metal basecontact 19 is deposited by electron-beam evaporation (FIG. 8), and thecollector layer 12 and subcollector layer 11 are defined by dry etching(FIG. 9). Finally, the metal collector contact 20 is deposited byelectron-beam evaporation (FIG. 10.)

In order to illustrate the advantages of the SL-HBT 10, the constructionand performance of a prior-art device, a heterojunction bipolartransistor (HBT), will also be described. Referring to FIG. 11, there isshown a vertical cross-section of a HBT indicated generally by 50. TheHBT 50 incorporates the following semiconductor layers in the followingorder, each in contact and forming a junction with the next, the firstlayer being in contact with a 500 μm thick undoped GaAs substrate:

a subcollector layer 51,

a collector layer 52,

a base layer 53,

an emitter layer 54,

an emitter electrode layer 55, and

an electrode layer 57.

The HBT 50 incorporates the following metal contacts:

a metal emitter contact 58 in contact with the electrode layer 57,

a metal base contact 59 in contact with the base layer 53, and

a metal collector contact 60 in contact with the subcollector layer 51.

Layers 54 to 57 and the metal emitter contact 58 constitute the emittermesa 61.

The HBT 50 has the same external dimensions (not shown) t and b to f asdefined earlier for the SL-HBT 10. FIG. 12 shows a table of the layerstructure of the wafer from which the HBT 50 is made, giving thethickness, composition and doping density of each of the layers 51 to56. The layers 51 to 56 are grown entirely by MOVPE. Layers 51 to 55 areas nearly as possible identical to those of the SL-HBT 10. The electrodelayer 57 has a thickness of 0.8 μm, so that the total thickness of theepitaxial layers of the HBT 50 is the same as that of the SL-HBT 10.Layers 51 to 55 are at the same distance from the emitter contact 58 asthe layers 11 to 15 are from the metal emitter contact 18 in the SL-HBT10. A direct comparison of the performances of the SL-HBT 10 and the HBT50 may therefore be made. The wafer processing stage of the fabricationof the HBT 50 is identical to that for the SL-HBT 10.

The metals contacts 58, 59 and 60 are identical to the metal contacts18, 19 and 20.

Referring now to FIG. 13, there are shown five graphs of emitter current(le) in amps as a function of base-emitter bias (Vbe) in dc volts forfive separate SL-HBTs, such as 10. These graphs show large and abruptreductions in gradient, such as 60, indicating large increases in theresistances of the base-emitter junctions of the SL-HBTs. At criticalvalues of emitter current, such as 60, the emitter current is limited.In some cases there is also region of negative differential resistance,such as 61. FIG. 13 therefore demonstrates the current-limiting effectof the superlattice region 16. An ideal SL-HBT has an le versus Vbecharacteristic with a substantially linear first region of non-zeroslope m₁ between 0.25 and 1Ω⁻ and a second region with a slope m₂ in therange −0.05 m₁≦m₂≦+0.05 m₁. Ideally the critical emitter current densityis twice that of the optimum drive current density of the SL-HBT.

FIG. 14 shows graphs of the collector current (Ic) in amps as a functionof the collector-emitter bias (Vce) in dc volts for a single SL-HBT suchas 10, operating in the common emitter configuration, for a range ofbase currents (Ib) starting at zero and increasing in steps of 200 μA.The emitter-current-limiting behaviour is again clearly demonstrated bycurrent plateau regions such as 70 and regions of negative differentialresistance such as 71.

The radio-frequency (RF) characteristics of the SL-HBT 10 and of the HBT50 will now be described.

FIG. 15 shows graphs of the maximum frequency of oscillation of theSL-HBT 10 (Fmax) in GHz as a function of collector current-density (Jc)in amps per square centimeter, at two values of the collector-emitterbias, namely 1.1 volts (solid line) and 3 volts (dotted line). FIG. 16shows equivalent graphs for the HBT 50, except that a solid linerepresents the performance of the HBT 50 when the collector-emitter biasis 1.5 volts. FIGS. 15 and 16 show that the SL-HBT 10 has a maximumfrequency of oscillation comparable to that of the HBT 50 over theindicated range of collector current-density, and that the inclusion ofthe superlattice region 16 within the SL-HBT 10 does not compromise RFperformance any more than the inclusion of a fixed ballast resistor.

FIG. 17 shows the maximum available gain (MAG) of the SL-HBT 10 in dB at10 GHz as a function of collector current-density (Jc) in amps persquare centimeter for the same collector-emitter bias values as in FIG.15. FIG. 18 shows equivalent graphs for the HBT 50, at the same valuesof emitter-collector bias as in FIG. 16. FIGS. 17 and 18 illustrate thatthe presence of the superlattice region 16 in the SL-HBT 10 does notreduce the maximum available gain from that available in the HBT 50 whenthe collector current density is in the range 10³14 10⁴ A cm⁻².

FIG. 19 shows the dynamic emitter resistance (Re) of the SL-HBT 10 inohms as a function of collector current-density (Jc) in amps per squarecentimeter for the same collector-emitter bias values as in FIG. 15.FIG. 20 shows equivalent graphs for the HBT 50, at the same values ofemitter-collector bias as in FIG. 16. The values of the dynamic emitterresistance have been deduced using an equivalent circuit model. FIG. 20shows that the HBT 50 exhibits a gradual decrease in dynamic emitterresistance as the collector current density is increased over the rangeindicated. This is normal behaviour for a HBT such as 50. FIG. 19 showsthat the dynamic emitter resistance characteristics of the SL-HBT 10have sharp increases at points such as 80, indicating that the emittercurrent density is being limited to an approximately constant value bythe superlattice region 16.

FIG. 21 shows the base-emitter voltage (Vbe) of the SL-HBT 10 in voltsas a function of collector current-density (Jc) in amps per squarecentimeter for the same collector-emitter bias values as in FIG. 15.FIG. 22 shows equivalent graphs for the HBT 50, at the same values ofemitter-collector bias as in FIG. 16. FIG. 21 shows that as thecollector current density in the SL-HBT 10 increases, the increase indynamic emitter resistance is accompanied by corresponding increase inthe base-emitter voltage as the current limiting regime of thesuperlattice region 16 is approached. This effect, which does not occurin the HBT 50 and is therefore not seen in FIG. 22, opposes the thermalrunaway of the emitter current which leads to the failure of HBT devicessuch as 50.

Referring now to FIG. 23, there are shown power transfer characteristicsfor the SL-HBT 10 when operated for maximum output power. Thecharacteristics shown are the gain in dB, the power added efficiency(PAE) in %, the collector efficiency in %, and the collector current inmilliamps. These were obtained using RF input pulses having a durationof 450 ns and a 10% duty cycle. The output power was maximised usingautomated tuning equipment at each value of the RF input power. Each ofthese characteristics is shown as a function of the output power in dBm.The maximum output power for the SL-HBT 10 under these conditions is18.5 dBm corresponding to a gain of 1 dB. This result is comparable tothat obtainable from typical HBTS, such as 50. FIG. 22 shows that thecollector current (lc) does not rapidly increase as the maximum outputpower is approached, a feature that is present in HBTs such as 50, andindicates imminent destruction of the device. At the maximum outputpower of the SL-HBT 10, the collector current is 30% greater than itsminimum value (which occurs at a power output of 13 dBm) compared to aHBT such as 50, where it is 50 to 100% larger. This feature of theSL-HBT 10 is attributable to the current-limiting effect of thesuperlattice region 16. RF testing of the SL-HBT 10 may be carried outusing pulses having a duration up to 100 ns longer than those used totest the HBT 50, without causing destructive self-heating. This furtherillustrates the beneficial current-limiting effect of the superlatticeregion 16.

Whereas the SL-HBT 10 has a single emitter mesa 21 (i.e. it is asingle-finger bipolar transistor), the invention may be a multi-fingerbipolar transistor incorporating a plurality of emitter fingers each incontact with a common base layer and each incorporating a superlatticeregion.

The invention may alternatively be implemented as a single-fingerbipolar transistor incorporating a superlattice region within oradjacent the transistor collector or emitter for example. The transistorbase, emitter and collector may be of the same or different materials(homostructure or heterostructure). The superlattice avoids thermalrunaway occurring as a result of a local hot spot developing in thefinger, and this of course could happen in a multi-finger device.

The invention may also be in the form of a multi-finger bipolartransistor in which individual fingers or mesas of the deviceincorporate individual collector, base and emitter regions, each fingeror mesa being in contact with a common region connected to each emitterregion.

A hot electron transistor may be configured in accordance with theinvention. This transistor is a unipolar device; it may have a single-or multi-finger permeable base or a metal base, or it may be a hotelectron tunnelling transistor, in each case having a superlattice orsuperlattices integrated therein. Each superlattice may be integratedwithin the or as the case may be each transistor emitter or base orcollector. The invention may be implemented as a field effect transistor(FET), which for the purposes of this includes high-electron mobilitytransistors, (HEMT), pseudo-morphic HEMTs (PHEMT), MESFETs andheterojunction FET (HFET) in addition to more conventional FETs. Asuperlattice limiter may be incorporated into an FET or a bipolartransistor in accordance with the invention to provide benefits for anumber of types of circuit. It can be included in or adjacent to thecollector or emitter of a bipolar transistor or the drain or source ofan FET to provide current clipping within the natural current limit ofthe transistor (as previously described) and/or gain limiting at highsignal levels. In the prior art, current clipping involves driving abipolar transistor into saturation generating excess charge storage anddegrading gain-bandwidth. The like in an FET leads to significant andharmful forward-gate current and to additional charge storage.

The gain limiting effect is advantageous in circuits requiring acontrolled reduction in gain at high signal levels. This function isimportant for low-noise oscillators where lower phase noise is achievedby reduction of loop-gain at a stable oscillation condition. Prior artgain limiting requires an additional diode component. The use of anintegrated superlattice limiter in accordance with the invention allowsa reduced number of components to be used and can provide lower noise.

The gain limiting and current limiting functions of transistors of theinvention can provide an important benefit for the driver stages of apower amplifier. Here an abrupt transition from linear gain to saturatedoutput is desired for optimal amplifier operation. This allows driverstages to be correctly sized so as to maintain good efficiency. Thedesired behaviour is often not achieved in prior art amplifier designsand oversizing of driver stages is required to provide sufficient drivepower to the next stage.

A superlattice limiter may be incorporated into a two-terminalsemiconductor device such as a pn diode in accordance with theinvention, eg in the electrode region of the diode. A diode has apositive thermal coefficient, and the superlattice limiter providescurrent limiting against thermal runaway.

Referring now to FIG. 24, there is shown a vertical cross-section ofanother embodiment of the invention, namely asuperlattice-vertical-cavity surface-emitting laser (SL-VCSEL) indicatedgenerally by 100. The SL-VCSEL 100 incorporates successively disposedsemiconductor layers, the first layer being in contact with an n-typeGaAs substrate 104 and being the first layer of the first mirror region106. Each subsequent layer is in contact and forms a junction with tworespective layers adjacent to it. Details of the layers are as follows:

n-type layers constituting a first Bragg-mirror region 106,

an insulating layer 108,

an intrinsic first cladding layer 110,

an intrinsic optical gain layer 112,

an intrinsic second cladding layer 114,

p-type layers constituting a second Bragg-mirror region 116,

p-type layers constituting the superlattice region 118,

a first metal contact layer 102, and

a second metal contact layer 120.

The SL-VCSEL 100 is constructed using known techniques as described inrelation to the device 10. The diameter s of the mesa 122 may be in therange 5 μm to 20 μm. The first Bragg-mirror region 106 has a thicknessof 3500 nm and the second Bragg-mirror region 116 has a thickness of2700 nm. The intrinsic optical gain layer 112 has a thickness of 56 nmand may be a single or multiple quantum well structure. Current passingthrough the SL-VCSEL 100 is limited by the superlattice region 118 inthe same manner as described above. The semiconductor layers are of theAl_(x)Ga_(1−x)As material system, where x is in the range 0 to 1.

In operation the SL-VCSEL conducts a current between the two contacts102 and 120 through the intervening layers 104, 106 and 110 to 118. Thisproduces lasing between the mirror regions 106 and 116, but thermalrunaway in the SL-VCSEL 100 is inhibited by the non-linear resistanceprovided by the superlattice region 118.

Whereas the SL-VCSEL 100 has a single mesa 122, the invention may be anarray of SL-VCSELs having two or more mesas, wherein the individualmesas each incorporate a superlattice region and one more active laserregions.

The superlattice region 16 has a structure giving the SL-HBT 10 aconductance with a negative temperature dependence. The SL-HBT 10therefore has further mechanism which counteracts thermal runaway whichis temperature-sensitive rather than current-sensitive. Resistance isincreased if the device becomes hot, even if the critical current levelhas not been reached. This is also useful in devices of the inventionhaving more than one electrically parallel current-carrying element eachelement incorporating such a superlattice structure. Resistance isincreased first in hotter elements whilst cooler elements remainunaffected and suffer no unnecessary reduction in current. The criticalcurrent of the SL-HBT 10 also has a negative temperature dependence. Thecritical current of the SL-HBT 10 has a lower value when the device isat a higher temperature compared to when the device is at a lowertemperature. Thus in multi-element devices of the invention, hotterelements experience current limiting at a lower current level thancooler elements.

Examples of the invention have been described which incorporate IndiumGallium Phosphide and the Al_(x)Ga_(1−x) As material system. Othermaterial systems may be employed, such as Si_(x)Ge_(1−x), where x hasdiffering values. Suitable pairs of materials include n-type materialswith dissimilar conduction band energies and p-type materials withdissimilar valence band energies.

It is likely to be possible to implement the invention as a deviceincorporating one or more superlattices each having barrier layers ofGaN and quantum well layers of InN or InGaN. An example of such a deviceis a nitride semiconductor laser or laser array incorporating at leastone such superlattice.

A superlattice structure which is potentially suitable for a nitridesemiconductor laser includes twelve pairs of layers with n-type doping,each pair comprising a four monolayer thick GaN barrier layer and a sixmonolayer thick In_(0.1)Ga_(0.9)N quantum well layer. Doping densitiesfor the layers would need to be established by experiment in order toensure that the superlattice provides the required current limiting.Experimental determination of doping densities in superlattice layers iswell known in the art of semiconductor device fabrication. A suitabledoping density may be 5×10¹⁶ cm⁻³. A device of the invention is requiredto have a current versus voltage characteristic similar to thoseillustrated in FIG. 13, and this provides a test to determine suitabledoping densities for the layers of the superlattice, i.e. a device withsuitable doping densities has a current versus voltage characteristicwhich exhibits a change in resistance at a critical device current toprevent the device current from reaching an undesirable level. Thesuperlattice would probably have to be grown by MBE or chemical beamepitaxy (CBE) rather than by MOVPE as it requires a high degree of layerthickness resolution.

What is claimed is:
 1. A transistor comprising: an emitter incorporatinga superlattice structure; a base; and a collector wherein the transistorhas an emitter-current versus base-emitter voltage characteristic whichincludes a first region below a voltage corresponding to a criticalemitter-current and having a non-zero slope of average value m₁; asecond region at the voltage corresponding to the criticalemitter-current having a slope of less than m₁; and a third regioncomprising a current plateau above the voltage corresponding to thecritical emitter-current, the plateau having an average slope m₂ in therange −0.05 m₁≦m₂≦+0.05 m₁.
 2. A transistor according to claim 1characterised in that the emitter-current versus base-emitter voltagecharacteristic exhibits a conductance which has a negative temperaturedependence.
 3. A transistor according to claim 2 characterised in thatthe critical device current has a negative temperature dependence.
 4. Atransistor according to claim 1 characterised in that the criticaldevice current has a negative temperature dependence.
 5. A transistoraccording to claim 4 characterised in that it is a hot electrontransistor or a bipolar transistor.
 6. A transistor according to claim 5characterised in that it is incorporated in an amplifying circuit toprovide current-clipping of an input waveform.
 7. A transistor accordingto claim 6 characterised in that the amplifying circuit is a radiofrequency amplifying circuit.
 8. A transistor according to any precedingclaim characterised in that it includes a transistor base of indiumgallium phosphide together with layers of the Al_(x)Ga_(1−x)As materialsystem, where x=0, 0.15 or 0.33.